Semiconductor-on-insulator (SOI) technology is becoming increasingly important in semiconductor processing. A SOI substrate structure typically contains a buried insulator layer, which functions to electrically isolate a top semiconductor device layer from a base semiconductor substrate. Active devices, such as transistors, are typically formed in the top semiconductor device layer of the SOI substrate.
Devices formed using SOI technology (i.e., SOI devices) offer many advantages over their bulk counterparts, including, but not limited to: reduction of junction leakage, reduction of junction capacitance, reduction of short channel effects, better device performance, higher packing density, and lower voltage requirements.
It is therefore desirable to form SOI substrates from bulk semiconductor substrates. One conventional method for forming a SOI substrate from a bulk silicon substrate involves selective masking of certain regions on the surface of a bulk silicon substrate, followed by anodization to form porous silicon at unmasked regions on the silicon substrate surface. Silicon at the masked regions is not porified and therefore forms solid silicon pillars. A silicon layer is subsequently grown over both the porous and non-porous portions of the silicon substrate. By forming an opening in the subsequently grown silicon layer, the porous portions of the silicon substrate become exposed and can therefore be selectively removed to form hollow regions underneath the subsequently grown silicon layer, while the non-porous silicon pillars provide the necessary structural support for the silicon layer during this process. Finally, the hollow regions can be filled with an insulator material to form a buried insulator film underneath the silicon layer, thereby resulting in a SOI substrate.
FIG. 1A shows a top view of a SOI substrate formed by the above-described conventional method, while FIGS. 1B and 1C respectively show cross-sectional views of such a SOI substrate along line I and line II. Specifically, the conventional SOT substrate comprises a device region 2 located over a base substrate 12 and encircled by trench isolation regions 20. A semiconductor device layer 16 is located at the device region 2, with a gate dielectric layer 3 and gate electrodes 5 are located thereabove. The semiconductor device layer 16 is separated from the base substrate 12 by a buried insulator layer 14, thereby forming a SOI configuration. Silicon pillars 11 are located at edges of the device region 2, as shown in FIGS. 1A and 1C. The silicon pillars 11 provide structural support for the semiconductor device layer 16 before the buried insulator layer 14 is formed.
However, the silicon pillars 11 in the above-described conventional SOI substrate structure extend from the base substrate 12 through the buried insulator layer 14 to overlap with portions of the semiconductor device layer 16, as shown in FIG. 1C. The overlap portions between the silicon pillars 11 and the semiconductor device layer 16 behave more like bulk structures than SOI structures, which undermines the advantages offered by true SOI structures.
Further, the processing steps used for forming such a conventional SOI substrate structure inevitably involve alignment errors and process bias, which do not scale well. Therefore, when the device structure is scaled from 90 nm down to 45 nm, the device performance will be further compromised.
There is therefore a need for improved SOI substrates that can be formed using bulk semiconductor structures, without undermining the advantages of true SOI structures or compromising the device performance at device dimensions below 45 nm.
There is also a need for a simple and effective method of fabricating the improved SOI substrates.